• Dynamically Optimized Cache Sharing for CMP Architectures
  • In this research, I investigate the use of dynamically optimized cache sharing as a means of increasing performance of CMP architectures across various multi-process and multi-threaded workloads.
    
    Since this research is still in progress, I am choosing to defer the release of intermediate papers.  For more information, please contact me.
     
• Dynamically Adaptive Prepaging for Effective Virtual Memory Management
  • This research is focused on the design and evaluation of dynamically adaptive prepaging as a means for implementing virtual memory.  The ultimate goal of such a policy is to achieve a significant reduction in page faults across a broad range of workloads (multi-programmed and VM) and, in doing so, exploit high disk bandwidths while avoiding high disk latencies.
  • PowerPoint Presentation
  • Report: Dynamically Adaptive Prepaging
  • DAPsim Simulator
    • In order to evaluate my proposed concepts, I developed a trace-driven simulator in C++ called DAPsim
    • DAPsim has the following capabilities:
      • Maintains main memory page queues
      • Handles page references
      • Models dynamic prepage allocation, degree, and prediction method
      • Accumulates performance statistics (page misses, miss rate, reference trace characteristics, hit/miss trace, and disk transfers)
  • Please contact me for additional information.
     
• Design and Evaluation of Advanced Value Prediction Methods for Multi-Issue Super Scalar Pipelined Architectures
  • The purpose of this project was to design, simulate, and evaluate advanced value prediction methods for multi-issue pipelined architectures.
     
• Multi-channel Temperature Measurement with Telemetry
  • Goal: The goal of this project is to design and build hardware that will allow for real-time temperature monitoring of a ceramic unit passing through a kiln. Thermocouples will capture temperatures that will be sent wirelessly to a stationary hardware platform interfaced with a PC.
     
• Data and Branch Hazards in a 32-Bit RISC Processor
  • The purpose of this lab was to use a VHDL version of the MIPS2000 pipelined architecture as constructed in Lab 8 to study data and branch hazards.  The MIPS2000 pipelined architecture was then adapted to support forwarding, stalling, and a minimal form of branch prediction to counter these hazards.
     
• Designing the CPU of a 16-Bit RISC Processor with an Advanced Register-Based Microprogrammed State Machine Controller
  • The purpose of this lab was to study the CPU of a CISC computer.  When this lab was complete, a CISC CPU was constructed in VHDL and its instruction fetch sequence was simulated.  Construction of the CPU was carried out in three steps.  First, the Internal Architecture was designed using the MaxPlusII Graphic Editor.  Then, the CPU controller was constructed also using the Graphic Editor.  Finally, the CPU controller and Internal Architecture were wired together along with a few other components to form the CPU of the Sweet16 processor.
     
• MIPS2000 Data Sheet
  • I constructed this data sheet to describe the functional behavior of the 32-Bit CISC Processor I designed, the MIPS2000

Personal Work

• My Software
  • A suite of Automated Finance Solutions.
  • Useful C++ programs