Documents
This page contains published paper based on ALR testbed, testbed architecture and setup document, and Avnet board document.
Published Paper
Real-Time Performance Analysis of ALR
This paper describes hardware prototype ALR system to address ALR challenges including fast switching mechanism, and link switching time. This paper also reveals the measured power consumption and link rate switching times using ALR hardware prototype, and discusses challenges and solutions involved in a direct implementation. The measurements indicate that the switching time between link rates is on the order of milliseconds, which is at least 70 times larger than that assumed in previous software simulation based works. Using measured real-time measurements of link switching times, power, and energy consumption, this paper identify new considerations for future control policy development
Testbed Architecture.
ALR NIC architecture is based on the RICE programmable NIC. The host and NIC communication components, including DMA unit, SDRAM controller, PCI interface, have been removed to reduce resource consumption. The ALR MAC core is the focal point of ALR MAC handshake protocol implementation and generates the ALR control frames. We developed the ALR MAC core based on the tri-mode Ethernet MAC core available from Opencores. We removed some internal modules and added extra components to existing modules to incorporate the ALR functionality.
Avnet Board.
We utilized the Xilinx Virtex-II Pro development kit (XC2VP20-FF896) manufactured by Avnet Inc to develop stand-alone ALR NIC. Technical details and purchasing information are available from the Avnet Electronics Marketing web site. The user guide, board schematic, PHY specification documents, and reference design for Avnet board.
Project Cooperator
