This webpage starts with the ALR Testbed Setup, and decribes the whole architecture of the ALR -enabled NIC.

Testbed Setup

Avnet Virtex-II Pro Development Kit

Available from Avnet Electronics Marketing, this development board features a 64-bit, 66 MHz PCI interface, a 10/100/1000 Ethernet PHY, two FPGAs, and multiple on-board memory resources. The specific development board used must have the Xilinx XC2VP30 FPGA and is Avnet model number ADSXLX-V2PRO-DEVP30-6.

Xilinx USB JTAG Cable

The XilinxJTAG-USB cable provides an inexpensive, stand-alone USB-2 programming solution for Xilinx FPGA boards. The cable can work with any USB equipped computer, and it attaches to system boards using a standard 14-pins JTAG header. It can program any Xilinx device down to 1.5V, at speeds up to 10 times faster than a JTAG3 cable. It can used to load bitstream and firmware. Also, it can used together with chipscope for debugging.

RS232 Serial Cable

The RS232 serial cable provides the debugging output of the firmware to the console on hyperterminal and also the packet transmission results.

CAT5-E crossover Cable

This cable can provide 10/100/1000 connection between two Ethernet PHY, when they are inserted into the RJ-45 port

Linux Workstation

Two desktop workstations both running Linux OS to execute the firmware compiler and Xilinx FPGA tools, including Xilinx ISE , Xilinx EDK, and Xilinx Chipscope.

Xilinx ISE

The evaluation version of Xilinx ISE can be downloaded from the Xilinx Website. We develop ALR MAC core with the Xilinx ISE environment, and do the simulation and test on it.ISE also includes Impact software that downloads the compiled bitstream to the FPGA. Xilinx ISE is required for the EDK to function. (The inexpensive EDK merely provides a wrapper GUI, some scripts, and new IP for the ISE compilation tools). IThe free ISE WebPack, although not tested, should suffice for this purpose, and can be downloaded from the Xilinx website. Version 8.1i was used for development.

Xilinx EDK

The XilinxEmbedded Development Kit (EDK) is a suite of tools and IP that enables you to design a complete embedded processor system for implementation in a Xilinx Field Programmable Gate Array (FPGA) device The Xilinx EDK is used to recompile the FPGA bitstream and to update the hardware bitstream with the NIC loader firmware. The Xilinx EDK 8.1 must be used to be compatible with Xilinx ISE 8.1.We use the new IPs from EDK, including PowerPC, JTAG-UART interface, and PLB bus unit, DCM modules and BRAM.

Xilinx Chipscope

This software package is only used to debug the hardware during customization and is not necessary for normal operation of the Power Efficient NIC. But since using the chipscope will add the extra hardware logic to the system, one should be careful with the extra logic.

Hardware & Firmware & Downloadbit

FPGA bitstreams

FPGA bitstreams are provided for Virtex FPGAs to enable all necessary hardware functions, including the ALR MAC core, Ethernet Packet Generator, PowerPC, DCM and UART_JTAG interfaces.

FPGA verilog files and VHDL files

These files configure the hardware part of power efficient ALR-enabled NIC.If the hardware structure is required to be modified, these files are required to be modified.

Firmware

Firmware is provided for Power PC embedded system. It is used for controlling the operation of ALR NIC and output the debug report on serial port.

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