Overview
We make this ALR testbed available for the research community to test and perform experiments with ALR for further study. The testbed has been used to measure imporatnt parameters for ALR including the link rate switching time and link rate switching power. These parameters are of great significance for ALR control policy.
ALR enabled NIC (Standalone Version)
We developed a hardware prototype of an ALR-enabled NIC in order to analyze and evaluate the performance of ALR in terms of link rate switching time and power consumption. We utilized the Xilinx Virtex-II Pro development kit (XC2VP20-FF896) manufactured by Avnet Inc. The Avnet board includes a Xilinx Virtex-II Pro FPGA, a Spartan-IIE FPGA, flash memory, SRAM 256MB DDR SDRAM, a PCI interface, a 10/100/1000 Ethernet PHY, and RJ-45 Ethernet connector. We built our NIC architecture based on the RICE programmable NIC. We removed the DMA Unit, DDR controller, and Spartan bridge, since the communication between the NIC and host is not our research focus and resources are limited
Acknowledgement
“This is part of Energy Efficient Internet project funded byNational Science Foundation.”
Project Cooperator
