Over the years I have written many Perl scripts to accelerate the tape-out process. The scripts listed here are the most general ones. I characterized them based on their position in cell-based design flow. Please feel free to use or modify them, and let me know if you have any comment.

Standard Cell Library

cell_selector.pl : the foundry-provided libraries usually contain logic cells that target different design requirements (high density, high speed or low power). This script collects only the cells that satisfy your requirements, and then writes their detailed descriptions to a new .lib file.

Synthesis

buf_insertion.pl : sometimes you want to wrap IO ports with a specific type of buffer (either standard or custom-designed). This scripts reads in the synthesized netlists, extracts the IO specifications, and export the desired buffer/wire statements. Example: input (.v), output (.buf and .wire).

Place and Route

pin_expansion.pl : the .io file is used to specify the pin location for Cadence SOC Encounter tool. However, it can be very tedious to specify the location for multi-bit signals. This script takes signals in original .io file and expand them based on their number of bits. Example: input (.io), output (.io).