Microprocessor Design

My first experience with microprocessor design was during my M.Sc. in Computer and Information Science (CISE) at UF, where I worked closely with professors
J.-K. Peir (CS) on developing branch prediction scheme and cache organization.
I designed a novel branch predictor and participated in the 1st JILP Championship Branch Prediction Competition (CBP-1) sponsored by Intel.

Low-Power Standard Cell Library Development

I implemented and characterized the low-power standard cell libraries for AMI 0.6um and UMC130nm CMOS technology. I used Cadence Abstract Generator and Synopsys SignalStorm in the process. The libraries were functionally proved by numerous IC chip fabrications.

Digital Baseband

After coming to ECE, I collaborated with professor K. O and R. Bashirullah on the development and implementation of the digital baseband for a 24-GHz single chip radio, which can be utilized to build m&m sized disposable sensor node (uNode). The baseband demodulation algorithms were modeled using Xilinx System Generator, RTL-coded and functionally verified in NC-VHDL, and place&route'd using Cadence SOC Encounter.