################################################################################
#!/usr/bin/perl -w
#
# buf_insertion.pl - adds desired buffers to all the IO ports.
# You can copy and paste these generated buffer lines to the original netlist,
# and make sure in the synthesis script the 'dont touch' is set for this block. 
#
# By Chung-Ching Peng  http://plaza.ufl.edu/peng6808/asic.html
#
# For usage help: Type buf_insertion.pl with no parameters
#
################################################################################
if(@ARGV[0] eq "") {
  print "ERROR: Insufficient input fields\n";
  print "\n";
  print "Usage:unix> ./buf_insertion.pl <synthesized netlist> \n";
  print "\n";
  exit;
}

################################################################################
# Generate Buffer Statements
################################################################################
$i = 1;
$j = 1;
$in_count=0;
$out_count=0;
$module_found=0;
$buffer = "HDBUFD2"; # from UMC130 Library, change the buffer name as you wish
open(out,">@ARGV[0].buf") || die "Couldn't open output file.\n ";
open(out1,">@ARGV[0].wire") || die "Couldn't open output file.\n ";
print "-----------------\n";
print "output files are $ARGV[0].buf and $ARGV[0].wire \n";
print "-----------------\n";

################################################################################
# Main Codes
################################################################################
open(infile0,"<@ARGV[0]") || die "Couldn't open infile0. @ARGV[0]\n ";

while ($line = <infile0>) {
	
  if($line =~ /module/) { #try to find the keyword module, if not find,                    
    $module_found = 1;    #dont start anything
  } 
    
  if( $module_found == 1) {
    chomp($line);
    @lines = split(/\/\//, $line);

      $lines[0] =~ s/^(\s+)//; #remove space
      $myline = $myline.$lines[0];
      
      if($myline =~ /;/) {
        $compline = $myline;
        $myline = "";
        print "compline = $compline\n";
      }
      else {
        $compline = "";
      }
      
      if($compline =~ /^(input|output|inout)\s+(\[(\d+):(\d+)\])\s+(.*)/ ) { #multiple bits
        print "found 1=$1 1=$2 1=$3 1=$4 1=$5\n";
        #found input [13:0] 13 0 testDAC;
        @port_names = split(/;/, $5);
        if($1 eq 'input') {
        	$bit=$3;
          while($bit>=0) {
            print out "$buffer BI$in_count (.A($port_names[0]\[$bit]), .Z($port_names[0]_B[$bit]));\n";
            print out1 "wire $port_names[0]\_B[$bit];\n";
            $bit=$bit-1;
            $in_count=$in_count+1;
          }
        }
        elsif($1 eq 'output') {
        	$bit=$3;
          while($bit>=0) {
            print out "$buffer BO$out_count (.A($port_names[0]_B[$bit]), .Z($port_names[0]\[$bit]));\n";
            print out1 "wire $port_names[0]\_B[$bit];\n";
            $bit=$bit-1;
            $out_count=$out_count+1;
          }
        }
      }#if($compline =~ /(^input)\s+(\[(\d+):(\d+)\])\s+(.*)/ )


      elsif($compline =~ /^(input|output|inout)\s+(.*)/) { # single bit
      	$direction = $1;
        @port_names = split(/\,/, $2);
        if($direction eq 'input') {
          $direction = 'input';
        }
        elsif($direction eq 'output') {
          $direction = 'output';
        }
        foreach $element(@port_names) {
          $element =~ s/ //;
          $element =~ s/;//;
          if($direction eq 'input') {
             print out "$buffer BI$in_count (.A($element), .Z($element\_B));\n";
             print out1 "wire $element\_B;\n";
             $in_count=$in_count+1;
          }
          elsif($direction eq 'output') {
            print out "$buffer BO$out_count (.A($element\_B), .Z($element));\n";
            print out1 "wire $element\_B;\n";
            $out_count=$out_count+1;
          }
        }      	
      }
      
  }#( $module_found == 1)
  $i=$i+1;
} #while ($compline1 = <infile0>)


close(out);
print "-----------------\n";
print "output files are $ARGV[0].buf and $ARGV[0].wire \n";
print "-----------------\n";