Applications of MFCC and Vector Quantization in speaker recognition.
(Presented in International Conference- ISSP 2013, published in IEEE Xplore Digital Library, ISBN: 978-81-909376-6-5, pp-178-181)
In speaker recognition, most of the computation originates from the likelihood computations between feature vectors of the unknown speaker and the models in the database. In this paper, we concentrate on optimizing Mel Frequency Cepstral Coefficient (MFCC) for feature extraction and Vector Quantization (VQ) for feature modeling. We reduce the number of feature vectors by pre-quantizing the test sequence prior to matching, and number of speakers by ruling out unlikely speakers during recognition process. The two important parameters, Recognition rate and minimized Average Distance between the samples, depends on the codebook size and the number of cepstral coefficients. We find, that this approach yields significant performance when the changes are made in the number of mfcc's and the codebook size. Recognition rate is found to reach upto 89% and the distortion reduced upto 69%.
Design and simulation of virtual reconfigurable circuit for a Fault Tolerant System
(Presented in International Conference- ICRAIE 2014, published in IEEE Xplore Digital Library, ISBN: 978-1-4799-4041-7)
Evolvable Hardware (EHW) refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. This paper presents a new approach to on-line fault tolerance via reconfiguration of the Programmable Elements (PE) mapped onto field programmable gate arrays (FPGAs). A grid of PE is programmed on the FPGA structure. A complete hardware implementation of an evolvable combinational unit for FPGAs is then performed. The proposed combinational PE grid on FPGA is used as virtual reconfigurable circuit (VRC). Cartesian Genetic Programming (CGP), genetic operators are described in Verilog - HDL and used to reprogram the VRC. In all the cases the unit is able to evolve (i.e. to design) the required function automatically and autonomously, with a maximum delay of 22.82ns (when logic level is 16) which is 40% lower than previous attempts. The design parameters of the proposed architecture are also discussed. The fault detection, based on self-checking technique can detect the faults of PEs and routing interconnections in the FPGAs concurrently with the normal system work. After locating the faulty PE, the VRC will be reconfigured using reserved PEs.