Xin Fu
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Ph.D. Candidate
Advanced Computing and Information Systems Lab (ACIS)
Intelligent Design of Efficient Architectures Lab (IDEAL)
Department of Electrical and Computer Engineering
311
Tel: (352)392-3947
Fax: (352)392-5040
Email: xinfu AT ufl DOT edu
Education
- Ph.D. Candidate, Department of Electrical and Computer
Engineering, University of Florida,
- Graduate Studies, Computer
Software and Theory,
- B.S., Computer Science,
Research Interests
- Computer Architecture, Processor Microarchitecture, Reliability, Nanoscale technology scaling, Performance modeling, Benchmarking and Analysis.
Projects
- Sim-SODA Development
Sim-SODA (SOftware Dependability Analysis),
built on top of the Sim-Alpha tool sets, is the first unified simulation framework for
high-performance microprocessor reliability estimation in the presence of soft
errors. I took the responsibility to
develop the entire Sim-SODA framework, which
requires heavy modifications of the Sim-Alpha code
and incorporates architecture vulnerability computing methods for heterogeneous
microarchitecture structures. Sim-SODA is available
at http://www.ideal.ece.ufl.edu/sim-soda.
It has been used by
- Sim-SODA Extension for SMT architectures
The Sim-SODA SMT extension is the first framework to estimate architectural and microarchitectural effects of soft errors on simultaneous multithreaded architectures. My responsibility was building the interface between Sim-SODA and the SMT processor simulator.
- Program Vulnerability Phase Characterization
The objective is to explore methods that can effectively characterize microarchitectural vulnerability phase behavior for reliable processor architecture design. I observed that single performance metric can not capture vulnerability phase behavior and evaluated the efficiency of program vulnerability phase classification methods using program-code structure and run-time events.
- Issue Queue Reliability Improvement in SMT architecture
Issue queue is a key microarchitecture structure to exploit ILP and TLP, it becomes more susceptible to soft errors in SMT architecture. I proposed two effective methodologies in issue queue reliability improvement, one is dynamically controlling issue queue utilization, and the other is operand readiness-based instruction dispatch.
- Circuit and Microarchitecture Techniques Combination for SMT
processor Reliability Improvement
Techniques for structures’ reliability improvement in SMT processors exist on both circuit and microarchitecture levels, but there are relatively few studies that cost-effectively integrate them together. I bridged the gap by proposing combined both circuit and microarchitecture techniques to leverage their advantage while overcoming the disadvantages. The combined techniques achieve significant reliability improvement in multithreaded environment.
- Characterizing and Mitigating Microarchitecture Soft Error
Vulnerability in the Presence of Process Variation
As transistor process technology approaches the nanometer scale, process variation significantly affects chip performance and power. However, the impact of process variation on soft error vulnerability is not well studied. I characterized the microarchitecture soft error vulnerability in the presence of process variation, I proposed two techniques that work at fine grain (entry-based) and coarse grain (structure-based) levels to mitigate the deleterious impact of PV on reliability and maintain optimal vulnerability, performance, and power trade-offs.
- NBTI Tolerant Microarchitecture Design in the Presence of Process
Variation
Negative bias temperature instability (NBTI), which reduces the lifetime of PMOS transistors, is becoming a growing reliability concern for sub-micrometer CMOS technologies. Process variation introduced by nano-scale device fabrication inaccuracy can exacerbate the PMOS transistor wear-out problem and further reduce the reliable lifetime of microprocessors. I proposed three microarchitecture NBTI reliability enhancements in the presence of process variation which effectively mitigate the detrimental impact of PV and NBTI simultaneously, while achieving good trade-offs among chip performance, power, lifetime, and area overhead.
Publications
- Xin Fu, Tao Li, and José Fortes, Soft Error Vulnerability Aware Process Variation Mitigation, International Symposium on High-Performance Computer Architecture (HPCA), February 2009
- Xin Fu, Tao Li, and José Fortes, NBTI Tolerant Microarchitecture Design in the Presence of Process Variation, International Symposium on Microarchitecture (MICRO), November 2008
- Xin Fu, Tao Li and José Fortes, ORBIT: Effective Instruction Queue Soft-error Vulnerability Mitigation on Simultaneous Multithreaded Architectures using Operand Readiness-based Instruction Dispatch, International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), October 2008
- Xin Fu, Wangyuan Zhang, Tao Li, and José Fortes, Optimizing Instruction Queue Reliability to Soft Error on Simultaneous Multithreaded Architectures, International Conference on Parallel Processing (ICPP), September 2008.
- Xin Fu, Tao Li, and José Fortes, Combined Circuit and Microarchitecture Techniques for Effective Soft Error Robustness in SMT processors, International Conference on Dependable Systems and Networks (DSN), June 2008. [PDF]
- Wangyuan Zhang, Xin Fu, Tao Li, and José Fortes, An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures, International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2007. [PDF]
- Xin Fu, James Poe, Tao Li, and José Fortes, Characterizing
Microarchitecture Soft Error Vulnerability Phase Behavior,
International Symposium on Modeling, Analysis, and Simulation of Computer
and Telecommunication Systems, September 2006. [PDF] [slides]
- Xin Fu, Tao Li, and José Fortes, Sim-SODA:
A Unified Framework for Architectural Level Software Reliability Analysis,
Workshop on Modeling, Benchmarking and Simulation (Held in conjunction
with International Symposium on Computer Architecture), June 2006.[PDF]
[slides]