# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2010 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
# Date created = 20:23:23  February 26, 2011
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		Lab4_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY MAX3000A
set_global_assignment -name DEVICE "EPM3064ALC44-10"
set_global_assignment -name TOP_LEVEL_ENTITY Lab4
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:23:23  FEBRUARY 26, 2011"
set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name BDF_FILE Lab4.bdf
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name BDF_FILE LatchMem.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE Lab4.vwf
set_global_assignment -name BDF_FILE FlipFlop.bdf
set_location_assignment PIN_20 -to LatchEnable
set_location_assignment PIN_39 -to A13
set_location_assignment PIN_21 -to FlipFlopEnable
set_location_assignment PIN_41 -to A15
set_location_assignment PIN_37 -to A12
set_location_assignment PIN_8 -to XRD
set_location_assignment PIN_6 -to WE
set_location_assignment PIN_40 -to A14
set_location_assignment PIN_34 -to A11
set_location_assignment PIN_12 -to XZCS0
set_location_assignment PIN_43 -to XCLKIN
set_location_assignment PIN_19 -to MemoryEnable
set_location_assignment PIN_14 -to A19
set_location_assignment PIN_11 -to A18
set_location_assignment PIN_16 -to A20
set_location_assignment PIN_9 -to XZCS7
set_location_assignment PIN_5 -to A17
set_location_assignment PIN_4 -to A16