{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 15 16:25:59 2011 " "Info: Processing started: Tue Mar 15 16:25:59 2011" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Lab4 -c Lab4 " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Lab4 -c Lab4" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TPD_RESULT" "A13 FlipFlopEnable 10.000 ns Longest " "Info: Longest tpd from source pin \"A13\" to destination pin \"FlipFlopEnable\" is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 1.400 ns A13 1 PIN PIN_39 3 " "Info: 1: + IC(0.000 ns) + CELL(1.400 ns) = 1.400 ns; Loc. = PIN_39; Fanout = 3; PIN Node = 'A13'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { A13 } "NODE_NAME" } } { "Lab4.bdf" "" { Schematic "C:/Users/Andrew/Documents/School/Spring 2011/4744/Lab4/Quartus/Lab4.bdf" { { 200 736 904 216 "A13" "" } { 192 176 272 208 "A13" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(4.500 ns) 8.200 ns inst12~3 2 COMB LC17 1 " "Info: 2: + IC(2.300 ns) + CELL(4.500 ns) = 8.200 ns; Loc. = LC17; Fanout = 1; COMB Node = 'inst12~3'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.800 ns" { A13 inst12~3 } "NODE_NAME" } } { "Lab4.bdf" "" { Schematic "C:/Users/Andrew/Documents/School/Spring 2011/4744/Lab4/Quartus/Lab4.bdf" { { 472 360 424 520 "inst12" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 10.000 ns FlipFlopEnable 3 PIN PIN_21 0 " "Info: 3: + IC(0.000 ns) + CELL(1.800 ns) = 10.000 ns; Loc. = PIN_21; Fanout = 0; PIN Node = 'FlipFlopEnable'" {  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { inst12~3 FlipFlopEnable } "NODE_NAME" } } { "Lab4.bdf" "" { Schematic "C:/Users/Andrew/Documents/School/Spring 2011/4744/Lab4/Quartus/Lab4.bdf" { { 360 688 864 376 "FlipFlopEnable" "" } { 480 424 528 496 "FlipFlopEnable" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.700 ns ( 77.00 % ) " "Info: Total cell delay = 7.700 ns ( 77.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns ( 23.00 % ) " "Info: Total interconnect delay = 2.300 ns ( 23.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1}  } { { "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/91sp2/quartus/bin/TimingClosureFloorplan.fld" "" "10.000 ns" { A13 inst12~3 FlipFlopEnable } "NODE_NAME" } } { "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/91sp2/quartus/bin/Technology_Viewer.qrui" "10.000 ns" { A13 {} A13~out {} inst12~3 {} FlipFlopEnable {} } { 0.000ns 0.000ns 2.300ns 0.000ns } { 0.000ns 1.400ns 4.500ns 1.800ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "162 " "Info: Peak virtual memory: 162 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 15 16:25:59 2011 " "Info: Processing ended: Tue Mar 15 16:25:59 2011" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Info: Total CPU time (on all processors): 00:00:00" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
